1. Field of the Invention
Embodiments of the invention relate to three-level unit inverter systems using bidirectional switches, and, in particular, to control technology for balancing output currents from inverter units.
2. Description of the Related Art
FIG. 9 is a circuit diagram of parallel-connected inverter units according to conventional technology disclosed in Japanese Unexamined Patent Application Publication No. 2006-296110 (also referred to herein as “Patent Document 1”). The circuit is composed of parallel-connected three inverter units UN1, UN2, and UN3 each employing two-level inverter circuit. The main circuit of a single-phase inverter includes four IGBTs and the main circuit of a three-phase inverter includes six IGBTs. The following description, however, is done for one phase only. Since the internal construction of each unit is similar, the description is made about the unit 1, UN1. In each inverter unit, a local control circuit LC0, receives a common ON/OFF signal from a main controller MC0 and gives ON/OFF signals to IGBTs Q1 and Q2 of the main circuit through a current balance controlling circuit and a gate driving circuit. The main circuit comprises: a capacitor C0 functioning as a DC supply, a series circuit of the IGBTs Q1 and Q2 connected in parallel with the capacitor C0, an AC filter consisting of a reactor L1 and a capacitor C3, a reactor L2 for unit parallel connection, and a current detector CT, the AC filter, the reactor L2, and the current detector CT being connected between a load LD and the series-connection point of the IGBTs Q1 and Q2.
The following describes about current balance control for the circuit of this construction. An output voltage of the current detector CT for inverter output current detection is amplified by a current amplifier G1 and the output voltage of the current amplifier G1 is connected, through a current detection resistor RI, between the inverter units via connection wires A. Connection wires B makes connection between the ground potentials GND of the local control circuits of the units. In this construction, the electric potential of the connection wire A is an average value of the output voltages of the current detectors, for equal resistance of the current detection resistors RI of the units. This averaged output voltage is proportional to the average value of output current of all units. The voltage across the resistor RI in a unit is a voltage proportional to the deviation in current of the current value in the unit concerned from the averaged current value over all units. This voltage is detected by an output current deviation detecting amplifier G2, which is a differential amplifier. The output of the differential amplifier G2 is given directly to an ON delay circuit DL1 for adjusting an ON pulse width of the IGBT Q1 and given through an inverter IN1 to an ON delay circuit DL2 for adjusting an ON pulse width of the IGBT Q2.
In this construction, in the case of a positive current deviation, or a larger output current value than the average current value, adjustment is conducted to shorten the ON pulse width of the upper arm IGBT Q1; in the case of a negative current deviation, or a smaller output current value than the average current value, adjustment is conducted to shorten the ON pulse width of the lower arm IGBT Q2. This adjustment makes the output current of the unit concerned closer to the average current value of all units. The operation described above is conducted individually with each unit to balance the output current among the units.
FIG. 10 shows an example of circuit construction of the three-phase, three-level inverter using bidirectional switches disclosed in Japanese Unexamined Patent Application Publication No. 2008-193779 (also referred to herein as “Patent Document 2”) and FIG. 11 shows an example of operation of the inverter. Referring to FIG. 10, the series circuit of capacitors C1 and C2 functions as a DC power supply having a positive terminal P, a negative terminal N, and a neutral terminal M. One phase of the circuit comprises a series circuit of an upper arm IGBT and a lower arm IGBT, and a bidirectional switch connected between the series connection point of the upper and lower arm IGBTs and the neutral terminal M of the DC power supply. The U phase circuit includes IGBTs Qu1 through Qu4 and diodes Du1 and Du2; the V phase circuit includes IGBTs Qv1 through Qv4 and diodes Dv1 and Dv2; and the W phase circuit includes IGBTs Qw1 through Qw4 and diodes Dw1 and Dw2. Bidirectional switches are constructed by the antiparallel-connection of the IGBTs Qu3 and Qu4, by the antiparallel-connection of the IGBTs Qv3 and Qv4, and by the antiparallel connection of the IGBTs Qw3 and Qw4. Between the series connection point of the IGBTs and the AC output terminal in each phase circuit, an AC filter and a reactor for parallel connection are connected. The AC filters are composed of: Lu1 and Cu for the U phase, Lv1 and Cv for the V phase, and Lw1 and Cw for the W phase. The capacitors are connected in a configuration of the star connection. The reactors for parallel connection are Lu2 for the U phase, Lv2 for the V phase, and Lw2 for the W phase.
The following describes, referring to FIG. 11, pulse patterns for one phase of the three-level inverter with the construction described above. In the one phase circuit in the following description, Q1 and Q2 designate the positive terminal P side IGBT and the negative terminal N side IGBT, respectively, of the IGBT series circuit connected between the positive terminal P and the negative terminal N of the DC power supply; and Q3 and Q4 designate the IGBT for carrying a current toward the neutral terminal of the DC power supply and the IGBT for carrying a current toward the series connection point of the IGBT series circuit, respectively, in the bidirectional switch connected between the neutral terminal of the DC power supply and the series connection point of the IGBT series circuit.
In this inverter, as shown in FIG. 11, a positive voltage is delivered by turning alternately the IGBT Q1 and the IGBT Q3 ON/OFF while holding the IGBT Q4 in the ON state. A negative voltage is delivered by turning alternately the IGBT Q2 and the IGBT Q4 ON/OFF while holding the IGBT Q3 in the ON state.
As can be seen from this operation principle, the IGBTs Q1 and Q3 operate as a half-bridge inverter to deliver a positive voltage in this three-level inverter, and the IGBTs Q2 and Q4 operate as a half-bridge inverter to deliver a negative voltage.
The IGBTs Q3 and Q4 composing the bidirectional switch in this circuit are subjected, between the emitter and collector thereof, to a high voltage, which is the voltage between the positive terminal P and the neutral terminal M or the voltage between the neutral terminal M and the negative terminal N. Accordingly, the IGBTs need to be special type of IGBTs, reverse-blocking IGBTs, exhibiting high withstand voltage between emitter and collector. This is the reason why this circuit has been practically applied only in recent years.
The output terminal delivers three levels of voltages: an electric potential at the positive terminal P of the DC power supply corresponding to turning ON of the IGBT Q1, an electric potential at the neutral terminal corresponding to turning ON of the bidirectional switch, and an electric potential at the negative terminal N corresponding to turning ON of the IGBT Q2.
A problem in the art includes the inability to ensure balance of output current between the inverter units in the unit type inverters employing a three-level inverter circuit in parallel operation.